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FPGA Development Boards

Spartan CPLD

TThe XC95108 is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of six 36V18 Function Blocks, providing 2,400 usable gates with propagation delays of 7.5 ns. Power dissipation can be reduced in the XC95108 by con-figuring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize power dissipation.

Block Diagram

Features

  • 108 macrocells with 2400 usable gates.
  • 3.3 V or 5 V I/O capability.
  • Supports parallel programming of more than one XC9500 concurrently.
  • Extensive IEEE Std 1149.1 boundary-scan (JTAG) support.
  • 5 V in-system programmable (ISP)
    • Endurance of 10,000 program/erase cycles.
    • Program/erase over full commercial voltage and temperature range.
  • Flexible 36V18 Function Block
    • 90 product terms drive any or all of 18 macrocells within Function Block.
    • Global and product term clocks, output enables, set and reset signals.

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